Improved algorithm for floating point multiplication

Floating point multiplication is one of the most frequently used arithmetic operation in a wide variety of applications, but the high memory and speed requirement of the IEEE-754 standard floating point multiplier prohibits its implementation in many systems which requires fast computing, such as in wireless sensors and in real time applications. This paper presents an improved algorithm for the floating point multiplier which provides a better performance in terms of time requirement for the implementation. This floating point multiplier is implemented and synthesized on Xilinx Spartan-3E FPGA.