Performance efficient FFT processor design

This paper proposes a FFT processor design for DAB and WiMAX applications whose efficiency is improved in terms of performance. The design is optimized for power. The 2D 256 point FFT employs Radix-16 algorithm which significantly minimizes the number of complex computations. The architecture is pipelined, with 10 bit real and imaginary inputs. The proposed pipelined FFT architecture has the advantage of reduced computational complexity along with less power consumption. The design makes use of the constant multipliers that were successfully designed and implemented to reduce the hardware complexity and speed was improved to a greater extent when compared with the existing constant multipliers. Compared with the few existing FFT processors, the synthesized results shows that the designed FFT processor reduces the power to a greater extent.