Low-Loss SOI-LIGBT With Dual Deep-Oxide Trenches

A 500-V silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) is proposed and investigated for the first time. The device features dual deep oxide trenches (DDOTs) formed in the drift region. The DDOT assists in sustaining the electric potential from the collector, which enables the SOI-LIGBT to reduce its drift region length. At the same breakdown voltage of 560 V, the drift region length is reduced from 47 μm for the conventional SOI-LIGBT to 23.4 μm for the proposed SOI-LIGBT. Due to the small-sized drift region, decreased amount of stored carrier and fast depletion of the drift region during the turn-off process are realized. The experiments demonstrate that the proposed SOI-LIGBT exhibits a superior tradeoff between turn-off loss (EOFF) and on-state voltage drop (VON) to the conventional SOI-LIGBT. EOFF of the proposed DDOT SOI-LIGBT is 36.9% lower than that of the conventional SOI-LIGBT at the same VON of 1.61 V. The DDOT can be fabricated simultaneously with the formation of the isolation trenches in a developed SOI bipolar-CMOS-DMOS-IGBT process.