Hardware implementation for permutation function of multiplication-hardened sponge BlaMka

In the information security field, varions algorithms are applied to provide users with a variety of security services. Although many of the algorithms are implemented in software, there is a rapidly growing demand for hardware implementations. The BlaMka algorithm is a cryptographic sponge algorithm, used in password hashing schemes (PHS) such as Lyra2 and Argon2, which are algorithms that generate a pseudo-random sequence of bits from a particular secret value. BlaMka was proposed as a modification of Blake2b algorithm by including multiplications in some stages of its implementation, specifically in its permutation function, aiming to reduce its performance in hardware platforms. As far as we are concerned, there is no hardware implementation for the BlaMka algorithm. Thus, this work presents a hardware implementation for the permutation function of BlaMka, which is the structure that contains multiplications, with some different architectures to address the trade-off between latency, area and power, besides verifying the impact of the inclusion of multiplications in its performance compared with a hardware implementation for the permutation function of Blake2b. All the circuits presented herein were described using VHDL language and synthesized for ASICs using the tools and the 90nm cell library provided by Synopsys. Combinational and sequential circuits were synthesized covering a range of possible choices taking into account the throughput, and the costs for area and power. The results for throughput ranged from 0.907 Gbps to 2.426 Gbps, area utilization ranged from 14.13 kGE to 52.82 kGE, and power consumption ranged from 0.384 mW to 98.462 mW. The results were compared to an implementation of the permutation function of Blake2b, verifying that the performance decrease is quite marked when multiplications are included in the permutation function.