Analysis of break-even time for nonvolatile SRAM with SOTB technology

Energy performance of nonvolatile power-gating (NVPG) that is a power-gating technique with nonvolatile state/data retention is demonstrated for nonvolatile SRAM (NV-SRAM) with spintronics retention and silicon-on-thin-BOX (SOTB) CMOS technologies. The NV-SRAM cell consists of an ordinary 6T cell and two magnetic tunnel junctions (for nonvolatile retention) with two pass-transistors. The cell and array architectures for leakage power reduction are developed, and the SOTB CMOS technology is used for the peripheral circuits to reduce the shut-down leakage. The break-even time (BET) that is an energy-performance index of NVPG is analytically formulated for a NV-SRAM array with its peripheral circuits. The BET behavior with respect to the cell/array architectures and the effect of the peripheral circuits are systematically analyzed using circuit parameters extracted from an implemented NV-SRAM.