Impact of Traps and Strain on Optimized n- and p-Type TFETs Integrated on the Same InAs/AlGaSb Technology Platform

A simulation study on the impact of interface traps and strain on the I-V characteristics of co-optimized p- and n-type tunnel FETs (TFETs) realized on the same InAs/Al
_0.05
Ga
_0.95
Sb technology platform is carried out, using a full-quantum ballistic simulator. In order to capture the effect of interface/border traps on the device electrostatics consistently with carrier degeneracy and ballistic transport, the classical Shockley-Read-Hall theory has been properly generalized. The effect of an experimental D
_it
distribution of a high-k gate stacks on InAs has been investigated. Unfortunately, traps induce a significant reduction of the ON-state current. However, it turns out that localized strain at the source/channel heterojunction caused by lattice mismatch is able to induce for the n-type TFET, a performance enhancement with respect to the ideal device even in the presence of traps. On the contrary, for the p-type one, a current degradation ≃18% is observed.