An FPGA implementation of a custom JPEG image decoder SoC module

An important feature of today's mobile devices is their ability to capture and display high resolution photos in an acceptable amount of time. These images are stored in flash memory on the mobile device using the JPEG codec which is almost a quarter of a century old but remains the industry standard. With increasing pixel counts on both mobile image sensors and screens, software solutions will struggle in their ability to decode JPEG image data in a reasonable time since they rely solely on increasing CPU power. The need is becoming clearer for hardware acceleration to replace the CPU when decoding large images. This paper presents a System-on-Chip (SoC) module that is able to relieve the CPU of the computationally intense task of decoding a JPEG image. This SoC module was developed and tested on Xilinx Zynq (a device which integrates an ARM dual core 667 MHz Cortex A9 CPU and an Artix-7 FPGA). The SoC module operating at 50 MHz was able to outperform software running on the onboard CPU by an average of 4.25 times while being more accurate to the original image. The speed up is attributed to a novel Huffman decoder which operates in a single cycle.