Design Space Exploration of Hysteresis-Free HfZrOx-Based Negative Capacitance FETs

In this letter, we investigate the design space of hysteresis-free negative capacitance FETs (NCFETs) by performing a cross-architecture analysis using HfZrO
_x
ferroelectric (FE-HZO) integrated on bulk MOSFET, fully depleted SOI-FETs, and sub-10-nm FinFETs. Our simulation analysis shows that FDSOI and FinFET configurations greatly benefit the NCFET performance due to their undoped body and improved gate-control, which enables better capacitance matching with the ferroelectric. A low-voltage NC-FinFET operating down to 0.25 V is predicted using ultra-thin 3-nm FE-HZO.