SI analysis of DDR bus during read/write operation transitions

Traditionally, the Read and Write operations of (LP)DDRx DQ busses have been analyzed independently. Transitions from one operation to another have usually been prioritized lower. At lower speeds, this prioritization might be justified, but at the higher speeds of (LP)dDR4, this comes into question. The SI effects between operations make it very important to simulate at higher speeds. Such analysis will require methodologies and modeling approaches beyond what has traditionally been practiced. This paper investigates the conditions under which an (LP)DDR bus's SI will be impacted by operation transitions and details how to perform simulations to handle such conditions.