An FPGA-based radiation tolerant SmallSat Computer System

This paper describes the design and testing of a radiation tolerant, low-cost computer system for use in small satellites. The computer is implemented on a modern Field Programmable Gate Array, which enables the novel fault mitigation strategy to be deployed on a commercial part, thus reducing the cost of the system. Using a modern processing node also provides increased computational performance and power efficiency. Our computer system has been in development at Montana State University for the past 8 years and has undergone a series of technology demonstrations to increase its technical readiness level. These include high energy particle bombardment at the Texas A&M Radiation Effects Facility, 8 high altitude balloon flights to 30km, and two sounding rocket flights to altitudes greater than 120km. This computer is scheduled for a demonstration onboard the International Space Station at the end of 2016 and for two stand-alone small satellite missions in low earth orbit in 2017. This paper will describe the design, testing, and characterization of our computer system in addition to the qualifications underway to prepare for the upcoming orbital demonstrations.