A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications

A novel complementary tunneling FET (C-TFET) has been designed and targeted for the low power and appropriate performance applications (Apps). In this new architecture of C-TFET, the drain and source (D/S) are configured as a staggered structure to increase the tunneling current, and the conventional p-i-n junction C-TFET has been modified as a p-n junction to further enhance the I
on
current. The results show that new design can achieve 310uA/um(n), 440uA/um(p) TFETs of I
on
, comparable to those of LP planar CMOS devices, 0.1 nA/um of I
off
, while excellent S.S.(<10mV/dec) at Vdd= 0.7V, which will be a promising candidate for the low-power and appropriate performance apps in the next decade.