Practical design considerations for an all-digital PLL in a digital car radio reception SoC

This paper addresses design considerations for an 4.4GHz all-digital PLL (ADPLL). This mixed-signal IP is used in a state-of-the-art wideband multi-tuner RF receiver integrated in a 65nm CMOS software-defined radio (SDR) SoC with automotive quality. It is therefore of extreme importance that the ADPLL not only meets the required phase noise, power supply rejection and speed specifications, among others, but also that it can coexist with other subsystems comprising the tuner, be tested with industrial automatic test equipment at acceptable cost, and that it operates reliably during the specified product's lifetime. This work describes simulation, interference, reliability, design-for-test (DfT) and design-for-manufacturability (DfM) aspects considered during the design process of the ADPLL.