Self-Aligned Double Patterning-Aware Detailed Routing With Double Via Insertion and Via Manufacturability Consideration

In 10nm technology node, self-aligned double patterning (SADP) and triple patterning lithography (TPL) allow us to achieve minimum wiring pitch of around 45nm. While metal layers can be printed by SADP, via layer manufacturing requires TPL to maintain design rules. SADP-aware detailed routing is proposed to ensure decomposability of metal layer patterns. However, its routing solution does not automatically guarantee TPL decomposable via layers. Vias have an inherently low reliability and via failure causes a great yield loss. Double via insertion (DVI) is an effective means to increase yield by reducing via failures. With the restriction of SADP design rules and consideration of TPL decomposability for via layers, DVI becomes a more challenging problem. In this paper, we consider DVI and via layer TPL manufacturability simultaneously in SADP-aware detailed routing. Both spacer-is-metal and spacer-is-dielectric types of SADP are considered. Furthermore, we tackle the TPL-aware DVI in postrouting stage. Both ILP and high-performance heuristic solutions are proposed. The experimental results demonstrate our router can obtain 100% routability and TPL decomposable via layers with reduced dead via count. Meanwhile, compared with the ILP approach to solve TPL-aware DVI problem, the heuristic approach can achieve similar solution quality and significant speedup.