Wide-I/O 3D-staked DRAM controller for near-data processing system

Nowadays, big data becomes one of most popular topics in the world. Analyzing these data needs large amount of memory accessing. For the requests of multi users, the memory need high bandwidth and high density. The power of moving data also needs to be considered in the big data generation. High density 3D-Stacked DRAM is the potential solution for the big data storage. By applying the through-silicon-vias (TSVs) technology in 3D-Stacked DRAM, the I/O pins between logic tiers and DRAM are at least 32× larger comparing the conventional DRAMs. In order to utilize the 3D-DRAM lager capacity and memory bandwidth, a new advanced 3-D memory controller is needed. In this paper, we present an energy-efficient DRAM controller to fully utilize the benefit offer for 3D-Stacked DRAM. The controller uses command rescheduling and rank interleaving to parallel the commands from multi users, and the self-refresh can save the power for 3D-Stacked DRAM refresh. Using near-data processing short the data path of transfer and makes the energy consumption decreased. The controller can realize the bandwidth improvement by 66.8%, and the execution time improvement by 40.08%. The energy consumption also decrease 27.18%.