Test strategies for the clock and power distribution networks in a multi-die IC

During a multi-die integration process, a number of known good dies are stitched together by die-to-die interconnects composed of TSVs (Through Silicon Vias) and/or die-to-die interconnecting wires. These die-to-die interconnects are not only used for signal transmission, but also for clock and power distribution. In this talk, we review some potential test methods that can be used for these two types of logistic die-to-die interconnects. Different from a simple pass or fail test, these methods often require a sophisticated characterization process that quantifies the effect of a parametric defect or the amount of variation. They can help diagnose the culprit of a failed IC to determine if it is due to the clock or power distribution network, and also suggest ways to recover from the failure when it is only parametric or variational.