Standard Cell Characterization for Reversible Logic

In the recent years, the circuit complexity has been on massive rise. Manual designing of the complex chips are no longer possible. This situation has led to the proliferation of automated Electronic Design Automation (EDA) tools. These have also have lead to the development of the standard cell design methodologies and the semi custom design solutions. The standard cell can be used for a particular function and this eases the design segment manpower and effort. Secondly, the complex circuits in dire necessity of low power operation, necessitates the non-conventional low power design methodologies such as the reversible logic. They play a significant role in the design of digital circuits due to its distinguishing feature of incurring low power dissipation. This paper portrays the design and standard cell characterization of the reversible logic. The Cadence® Liberate tool has been used in the designs and 45nm CMOS technology library files have been employed.