An enhanced approach to reduce test application time through limited shift operations in scan chains

Scan Chains in Design For Testability gained more prominence due to the increase in the complexity of the modern circuits. As the test time increases along with the number of memory elements in the circuit, new and improved methods are needed. Even though scan chains implementation effectively increases observability and controllability, a big portion of the time is wasted while shifting in and shifting out the test patterns through the scan chain. The proposed algorithm improves the test application time by using limited scan operations where the number of shifts is less than the actual length of the scan chain. Contrary to classic methods that do not provide any feedback to the test generator our algorithm uses an iterative procedure to generate suitable test vectors. The proposed algorithm uses modified shift procedures by searching for hard to detect faults and then rearranging test patterns and changing the shift procedures to achieve fault coverage in reduced number of clock cycles.