BPSim: An integrated missrate, area, and power simulator for branch predictor

When designing the branch predictors in processors, designers not only need to consider the prediction accuracy, but also should pay attention to the die-area occupied by the predictor, power consumption and other issues. Previous simulations of branch predictors have either only considered accuracy, or used low-speed full system simulators. We presents BPSim, a fast simulation environment for branch predictor based on trace driven, combining accuracy, area, and power consumption. Within this environment, the design parameters of the TAGE branch predictor with superior performance are automatically explored by the given RAM size and GHR length as input.