Cycle-accurate software modeling for RTL verification of embedded systems

Today's applications for HW/SW-systems, such as the Internet-of-Things, often demand SoC architectures where sophisticated firmware is running on fairly simple processors. Designers face the challenge of meeting high requirements for these systems regarding their efficiency and dependability under severe cost constraints. Targeting such applications this paper presents a new technique to generate a joint computational model for the hardware and its firmware. Generation of our computational model is interleaved with techniques from WCET analysis so that clock-cycle accuracy of the resulting model is achieved. As an application of our approach, we present how to generate a fast, cycle-accurate RTL simulation model that can replace the processor and its firmware in the RTL system description. Our experimental results show an acceleration by an order of magnitude when applying standard cycle-accurate RTL simulation to our modified design.