Physical Models of Planar Spiral Inductor Integrated on the High-Resistivity and Trap-Rich Silicon-on-Insulator Substrates

High-resistivity(HR) silicon-on-insulator (SOI) substrates provide low substrate loss, so planar spiral inductors integrated on them presenting higher quality factor (
$Q$
) than those on traditional Si substrates. However, the parasitic surface conduction (PSC) effect in the SOI substrate constitutes a conductive layer underneath the buried oxide layer, which deteriorates the inductors performance. This effect can be effectively eliminated by introducing a trap-rich layer. In this paper, physical models that can accurately characterize the behavior of inductors integrated on the HR and radio frequency enhanced signal integrity (RFeSI) SOI substrates are presented, and the analysis and evaluation of PSC effect on the performance of inductors, i.e., the inductance, the quality factor, the self-resonant frequency, and the frequency, where
$Q$
peaks, are shown. Planar spiral inductors integrated on HR and RFeSI SOI substrates are fabricated and measured, validating the feasibility of the models we use. The experiment results show that the value of
$Q$
and the frequency where it peaks can be improved significantly by eliminating the PSC effect. The temperature effects are also explored, showing that the PSC effect gets worse with raising temperature and accelerates the degradation rate of
$Q$
.