A cost-effective 8/spl times/8 2-D IDCT core processor with folded architecture

A dedicated cost-effective core processor of the 8/spl times/8 two-dimensional (2-D) inverse discrete transform (IDCT) architecture based on the direct realization approach is proposed. The folding scheme is developed to obtain a low gate-count and high throughput. The experimental result shows that the chip's throughput is one pixel per clock cycle with a structure of 78 K transistors, which reveals that the low cost of VLSI implementation is more attractive than most of previously reported chips. With 0.6 /spl mu/m CMOS, double metal technology, the chip is a standard-cell implementation and requires a core size of 4.4/spl times/2.8 mm/sup 2/, and is able to operate at a clock rate of more than 100 MHz.