Electrical-Spin Transduction for CMOS-Spintronic Interface and Long-Range Interconnects

We propose circuits for efficient transduction between electrical and spin signals and compare designs for long-range spintronic interconnects based on transducers and repeaters. This paper analytically analyzes the performance of spintronic all-spin logic (ASL) interconnects in terms of delay, area overhead, and energy dissipation, and validates the analysis by numerical simulations. The results of simulations show that compared to ASL repeaters, the proposed transducer-based interconnect achieves 5
${\times }$
shorter delay, 19
${\times }$
lower energy dissipation per bit per length, and a 9
${\times }$
smaller area-delay-power product for a 4
$\mu \text{m}$
long interconnect. We show that the proposed interconnect can operate under supply voltage values ranging from 300 to 950 mV and tunnel magnetoresistance values ranging from 131% to 450%.