Analyzing the Impact of Fault-Tolerance Methods in ARM Processors Under Soft Errors Running Linux and Parallelization APIs

This paper presents an analysis of the efficiency of traditional fault-tolerance methods on parallel systems running on top of Linux OS. It starts by studying the occurrence of software errors at systems presenting different levels of complexity, from sequential bare metal to parallel Linux applications. Then two traditional fault-tolerance mechanisms (triple modular redundancy and duplication with comparison variant) are applied to the applications and their efficiency analyzed. All cases were tested at the single and dual-core versions of an ARM Cortex-A9 processor that is embedded in many commercial system-on-a-chip. The OVP simulator platform is used to instantiate the processor model and to inject faults into the system. Faults are modeled as bit flips in the processor registers. Results show that traditional fault-tolerance algorithms are not efficient enough to protect a whole parallel system running on top of an operating system, given that the operating system itself is a major source of errors.