A High-Voltage “Quasi-p-LDMOS” Using Electrons as Carriers in Drift Region Applied for SPIC

A new type of “quasi-p-lateral diffused metal oxide semiconductor” (quasi-p-LDMOS), in which electrons are used as conductive carriers in the drift region is proposed. A floating electrode F is used in the “quasi-p-LDMOS” to transform the hole current into electron current. Then, by using an integrated low-voltage power and an inverter to control the electron current automatically, the specific on-resistance (R on,sp) is significantly reduced and the device can be successfully turned on and off. Simulation results show that the Ron,sp is 12.77 and 31 mΩ·cm
²
for a 349 and 630 V “quasi-p-LDMOS,” being only about 19.7% and 14.7% of a Triple-RESURF p-LDMOS, respectively. Moreover, the Ron,sp is even lower than that of a Triple-RESURF n-LDMOS at the same rated breakdown voltage. The figure of merit of the device is 3 to 7 times of that of state-of-the-arts. The “quasi-p-LDMOS” is designed as a low-side device in a new high-voltage CMOS circuit. By applying the “quasi-p-LDMOS” in the CMOS circuit, the total power loss is much lower than that of a conventional half-bridge circuit in a wide operating frequency. The “quasi-p-LDMOS” is suitable for smart power integrated circuit to improve both the integration level and system efficiency, and simplifies the circuit design.