Measurement of a clock-tuned digital non-Foster circuit for positive or negative digital capacitance

Theory and measured results are presented for a clock-tuned digital capacitor that provides digital implementation of a variable non-Foster negative capacitance or a variable positive capacitance. Unlike previous digital non-Foster capacitor designs, the proposed approach provides a variable capacitance without requiring changes to the signal processing hardware or embedded software. Instead, a single external clock provides simple control of the variable negative or positive capacitance of the circuit. Theoretical results are provided showing that predicted digital capacitance is inversely proportional to clock frequency, and associated parasitic resistance is determined by design parameters. Simulation results and prototype measurements confirm the underlying theory, and demonstrate the efficacy of the proposed approach.