Reliability-Enhanced Hybrid CMOS/MTJ Logic Circuit Architecture

Benefitting from its non-volatility, nearly infinite endurance, good scalability, and great CMOS compatibility, magnetic tunnel junction (MTJ) embedded in conventional CMOS logic circuits has been proposed as one potentially powerful solution to introduce non-volatility in today's programmable logic circuits, which is envisioned to achieve low power and high area efficiency. However, the recently proposed hybrid CMOS/MTJ logic circuits and prototypes based on such a logic-in-memory architecture suffers from a severe reliability issue, which is the precise transformation from MTJ resistance to electric signals due to its limited tunnel magnetoresistance ratio (TMR≤ 150%), i.e., the requirement of nearly zero sensing error for logic applications. In this paper, to overcome this sensing reliability issue, a novel sense amplifier (SA) with high sensing margin is proposed for such hybrid CMOS/MTJ logic circuit architecture. By using a commercial CMOS 40 nm design kit and a physics-based MTJ compact model, hybrid CMOS/MTJ transient and Monte Carlo statistic simulations have been conducted to demonstrate the functionality of the proposed SA and evaluate its performance, respectively.