A statistically robust methodology for optimized sample size determination for FPGA post-silicon validation

Due to sheer design complexity, it is nearly impossible today to detect and fix all bugs before manufacture. Post-silicon validation is becoming extremely important [1]. Since Field Programmable Gate Arrays (FPGAs) use a novel structure to implement programmability, FPGA silicon validation can be very time consuming. It is not unusual to see some measurements take several hours for each unit. It is hard to meet tight time-to-market requirements for a new product release if a redundant sample size is selected. However, an inadequate sample size may give misleading results which can cause serious quality risk. So determining the optimal sample size for FPGA silicon validation has now become a very critical process. This paper introduces a statistical method to determine the best sample size in FPGA post-silicon validation to achieve an optimum balance between the contradicting requirements for product time-to-market and quality coverage.