Study of safe operating area and improvement for power management integrated circuit

LDMOS (Lateral Double-diffused Metal Oxide Semiconductor) is widely used to smart power management IC, which can be attributed to its high operation voltage and high current driving capability. Furthermore, LDMOS is compatible with conventional CMOS processes. It will be much easier for IC foundries to make it by existing process flows. Operating at both a high drain voltage and a high current, LDMOS is more sensitive to hot carrier degradation than the devices with low operation voltages [1]. Thus, the LDMOS HC-SOA (Hot Carrier Safe Operating Area) is a major reliability concern and requires more attentions. In this paper, the HC-SOA's of conventional core and IO MOS are also illustrated to show different failure mechanisms and we focus on the detailed HC-SOA test method in practice. Additionally, we study the SOA contours for different cores, IO, NPMOS and LDMOS. Finally, we discuss the HC-SOA extension methods for LDMOS.