Design of comparator using Domino Logic and CMOS Logic

This paper presents implementation of 4 bit comparator circuit using Domino Logic (High speed Domino) and CMOS Logic. In CMOS Logic during inverter circuit operation when voltage level shifts from high to low and vice versa short circuit current occurs which leads to power loss. So Domino Logic is one of the power saving technique which helps to avoid this short circuit current and saves power consumption. So in this paper we have made a comparative analysis between the Domino logic and the CMOS logic for which we have used comparator as our reference circuit. As Domino Logic is well known for its power saving technique so the main parameter which we have considered in this paper is power. We also tried to fetch power consumption at different voltage level (voltage scaling) and at least 55% of power is saved by Domino Logic as compared to that of CMOS circuits. In this paper Generic 0.25u technology is used and EDA (Tanner tool version 16) is used to implement the circuit and for simulation purpose.