Flexible hardware architecture for LDPC encoder

Low density parity check (LDPC) codes are well known for their good error correction capability near to Shannon's limit and also due to parallel decoding possibility. The proposed work deals with design and FPGA implementation of flexible LDPC encoder using general and RU methods. LDPC encoder architecture with RU method encodes with propagation delay of 1.256ns less compare to general method. The flexible encoder designed with propagation delay of 5.208ns with 2/5,3/5. rates of code. Flexible Encoder designed can be capable of encoding for any rate and any length of the parity check matrix.