Optimization of Bulk Planar Junctionless Transistor using Work function, Device layer thickness and Channel doping concentration with OFF Current constraint

In this paper, the effect of three device parameters, gate electrode work function (WF), device layer/film thickness (T_c) and channel doping concentration (N_d), on DC parameters has been studied in 20 nm gate length Bulk Planar Junctionless Transistor (BPJLT) using Sentaurus TCAD simulator. Using the above device parameters (I_ON/I_OFF) ratio of the BPJLT is optimized with I_OFF constraint. The results are compared against the literature [1]. A gate electrode work function of 4.98 eV, film thickness of 8 nm and channel doping of 3.3×10¹⁹cm^-3 gives 29% increase in ION and (I_ON/I_OFF) ratio.