An efficient cache replacement algorithm for minimizing the error rate in L2-STT-MRAM caches

In the recent times, various challenges are being encountered during SRAM cache design and development which lead to a situation of converting the memory cell technologies into on-chip embedded caches. The current research statistics towards cache designing reveals that Spin Torque Transfer Magnetic RAMs, preferably termed as STT-MRAMs has become one of the most promising areas in the field of memory chip design. Hence, it gained a lot of attention from the researchers due to its dynamic direct map and data access policies for reducing the average cost i.e. time and energy optimization. Instead of having efficient main memory access capability, STT-MRAMs suffer due to high error rate caused during stochastic switching in write operations. Cache replacement algorithms play a significant role in minimizing the error rate in write operations. The proposed study aims to offer a theoretical and analytical modeling of an efficient cache replacement scheme to overcome the error as mentioned above in L2-STT-MRAM caches. The performance analysis of the proposed algorithm ensures its effectiveness in reducing the error rate and cost overheads as compared to the conventional LRU technique implemented on SRAM cells.