Test vector Generation using different logic regression method

Automatic Test Pattern Generation (ATPG) is used to determine test input sequence for digital circuit which distinguishes for the correct and faulty circuit behavior. These circuit behavios are caused by the internal and external defects. The circuit under test (CUT) gets the input test vectors from these ATPG. This test sets are compressed to reduce the test time. Different fault models of physical defects of the circuits are facilitates test generation. The Stuck-at faults and fault transition models are extensively used because of their expediency. In this paper two methods of logic regression have been designed in order to obtain random test patterns. In static method, test patterns are generated using a characteristic polynomial, in bit separation method, test patterns are obtained by separating odd and even bits.