Application of modified Petri Nets algorithm in digital IC design for combinational digital circuits simulation

This paper presents the use of modified Petri nets algorithm as a simulation engine for a logic simulator (Petri Logic Simulator). The tool was employed for the logic simulation of combinational digital circuits. Using modified Petri nets algorithm, it is possible to eliminate delta delay. Employed tool may propose more accurate simulation results through solving an issue of priority choice problem, when two or more events are to occur simultaneously.