A Hybrid Sampling Method for In-the-Loop Yield Estimation of Analog ICs in an Optimization Process

Analog integrated circuit sizing can be modeled as an optimization problem and solved by optimization heuristics. The resulting solution is dependent on the modeling strategy and on the performance estimation, which is done, in general, by electrical simulations. However, the optimized solution falls on the border of the design space, where a small variation in the device parameters affects the circuit performance. In order to address this issue during sizing steps, a Monte Carlo simulation is included in the optimization loop, leading in a computational effort increasing. This work analyses both Latin Hypercube and the traditional random sampling methods in order to reduce the number of Monte Carlo runs for minimizing the necessary time to estimate the resulting yield at each iteration of the optimization process. Based on these analysis a hybrid sampling method is proposed to lower the Monte Carlo processing time. The methodology is applied for the sizing of a two-stage Miller operational transconductance amplifier, showing advantages in terms of processing time and circuit performance while producing a more efficient search in the design space.