On the development of a high-level fault simulator for the analysis of performance faults on speculative modules

Speculative processors include performance oriented modules that improve the processor performance by exploiting speculation techniques in some time-consuming operations. The most common speculative modules in modern processors are branch prediction units, memory caches, load value speculation, and reorder buffers. Interestingly, about 40-50% of the processors area is devoted to these performance-oriented modules. Considering a faulty speculative module, the fault may only impact the processor performance even if not modifying the actual processor computation, then, providing always the correct results even if in a different computational time. These faults are usually called performance faults. However, in modern processors it is still difficult to identify this kind of faults. In this paper, we propose the creation of a simulation-based tool aiming at analyzing and characterizing the possible performance faults that may affect speculative modules, in particular Branch Prediction Units (BPUs). In addition, the proposed technique provides a first approach aiming at better identifying the faulty elements allowing a possible reconfiguration. The proposed approach and the performed experiments were implemented on a freely available high-level architectural simulator.