Incremental Analog‐to‐Digital Converters

This chapter discusses how integrated sensor interface circuits are required to prepare the analog sensor output for digital signal processing. Typical applications include digital voltmeters, image sensors, and biosensors. As expected, the response for minimum thermal output noise is constant, and the response for minimum quantization output noise is similar to a quadratic parabola. The result is the incremental A/D converter (IADC). The number of clock periods between resets determines the oversampling ratio. Compared to the delta‐sigma analog to digital converters (ADC), the IADC provides lower SNR, but it is easy to multiplex, has lower latency, and needs a much simpler digital filter. It is also less vulnerable to idle tones and instability. For low oversampling ratios, the SQNR cannot be significantly improved by raising the order of the loop‐filter, and high SQNR may only be obtained by using impractically high quantizer resolution. High‐order noise shaping may be obtained, while using only low‐order individual loops.