Circuit Design for Discrete‐Time Delta‐Sigma ADCs

This chapter examines circuits for switched‐capacitor sigma‐delta analog‐to‐digital converters (ADCs), using a simple low‐speed 1‐bit second‐order modulator to illustrate the primary design considerations. An ADC having a bandwidth of 1 kHz could be used as an on‐chip voltage monitor or as part of a low‐speed calibration engine. The designer should ensure that the amplifier has enough input common‐mode range to accommodate such errors. The folding connection between the output of the differential pair and the source of the opposite‐polarity cascodes provides a wide input common‐mode range, while the cascaded current sources in the output legs provide a high output impedance and hence high opamp gain. Behavioral modeling can be used to quantify the distortion resulting from a given gain curve, but it is more direct, and usually easier, to rely on transistor‐level simulations of the amplifier in the context of the modulator. The second amplifier can be a scaled‐down version of the first amplifier. The capacitors in the second stage are so much smaller than those in the first stage that a scaling factor of 10x appears reasonable.