A novel design of a Dual Functionality Read-Write driver for SRAM

Memory systems like Static Random Access Memories (SRAM) and Non Volatile Memories (NVM) thrive on area and power efficient designs. This paper presents a novel and a power proficient design of a Dual Functionality Read-Write (DFR-W) driver for SRAM sub-system. This design is integrated with a memory sub-system with an operating frequency of 1GHz in CMOS 65nm technology. It is then compared with a conventional memory architecture on grounds of power, area, leakage and speed of operation for varied memory capacities. DFR-W depicts a reduction of up to 35.58% in latching delay and of about 14% in writing time as compared to the conventional memory architecture. For the new design, there is a drastic decline in leakage current when the device is in hold mode. In DFR-W driver, leakage reduces to about 8.0844nA as compared to 22.833nA in the conventional design. The complete memory architecture with DFR-W driver shows a reduction of up to 6% in the power dissipation as compared to the conventional design. The proposed design performance is found way superior and efficient in terms of speed and power.