An early global routing framework for uniform wire distribution in SoCs

System-on-Chips (SoC) are being used to realize multipurpose devices such as mobile phones, consumer electronics which can connect over the internet. The design process including the physical design for an application specific SoC has become more complex due to large number of distinct functional modules. Existing physical design flow usually needs many iterations for successful design closure. In this paper, we propose a uniform wire distribution driven early global routing framework. The goal is to assist in obtaining an optimal routing solution for a given SoC floorplan such that the subsequent stages have fewer iterations. Based on the proposed congestion penalty, hierarchical routing order of the nets and a suitable routing region definition for a given floorplan, our method finds a solution with 100% routing completion, total wirelength within a constant bound of HPWL and no overflow in congestion for a given number of routing layers. We also estimate the number of vias incurred due to an existing minimal bend routing topology and uniform wire distribution for a set of routing layers. Experiments on IBM HB floorplanning benchmarks yield 45% improvement in average congestion with marginal increase in netlength, via count, and runtime for up to 8 layer HV routing. Congestion statistics for the critical routing layers such as M
₁
and M
₂
also show improvement.