An efficient transient thermal simulation methodology for Power Management IC designs

Power Management devices are becoming ubiquitous in every electronic system for achieving energy efficiency with constrained power/thermal budget. Multi-Function and Multi-Channel PMICs are becoming common design trend to support diverse voltage/power requirements of complex SoCs. In this paper, we present an approach to perform a full chip level thermal analysis with the capability to perform a detailed sub-modeling for electro-thermal analysis with Finite Element method and perform thermal-aware EM and stress analysis. The approach in transient thermal, thermal-aware EM and stress analyses includes the generation of thermal-aware chip power maps, conversion of converged thermal profiles in Power Devices to thermal loadings and detailed sub-modeling of on-chip structures for transient thermal, thermal-aware EM and thermal-induced stress analyses.