FPGA implementation of high speed vedic multiplier

Multiplication is an important fundamental function in arithmetic operations. Multiplication based operations such as Multiply and Accumulate unit (MAC), convolution, Fast Fourier Transform (FFT), filtering are widely used in signal processing applications. As, multiplication dominates the execution time of DSP systems, we need to develop high speed multipliers. Ancient Vedic mathematics facilitates the solution some to extent. In this paper, concept of Urdhwa Tiryagbhyam is used i.e., vertically and crosswise multiplication to implement 16×16 Bit Vedic multiplier. This technique reduces the delay in digital circuits. The Vedic multiplier is implemented in VHDL whereas synthesized and simulated using Xilinx ISE 8.1i.