Methods for TSVs placement in 3D Network-on-Chip

In the paper we describe F-medians searching algorithm for Three-dimensional (3D) Network-on-Chip (NoC) design. Modern 3D NoC development is complex and complicated task. Developer should solve different problems: Intellectual Property (IP) blocks placement on the die, organization of vertical links between dies in the 3D stack, energy consumption limitation, system performance improvement. We consider approaches for placement vertical links on the die and suggest a new methods that are based on the P-median problem.