Operating frequency improvement on FPGA implementation of a pipeline large-FFT processor

In this paper, circuit complexity reduction in FPGA implementation of large N-point Radix-2
²
FFT with single-path delay feedback architecture is reported. Memory requirement of the FFT in the FPGA consists of two parts, the RAM data storage of the feedback in each stage of the data flow and the twiddle factors prepared as ROM for each complex multiplication. Through address rearrangement, the ROM sizes for the twiddle factors are significantly reduced with the removal of redundancy. The reduction ratio is about 1/3(log
₄
N-1). As a result, the signal critical path is reduced and the system clock frequency is increased. The proposed architecture is validated by the implementations of 1K and 4K Radix-2
²
FFTs in an Altera Cyclone IV FPGA, EP4CGX22, which is the second lowest capacity FPGA of the low cost series. For the 1K- and 4K-point FFTs, the operating frequencies are 231.11 MHz and 215.75 MHz, respectively, approaching 250 MHz which is the speed limit of the I/O ports of the FPGA [1].