A new method of reconfigurable ADC using calibrated programmable slopes

The paper explores a new technique for improving and optimizing the resolution and conversion time of reconfigurable Analog to Digital Convertor (ADC) using programmable slopes. The most commonly used and simple way of analog to digital conversion using single slope technique requires two to the power of N number of bits (where N is ADC resolution) clock cycles to convert full scale voltage. As the number of bits increases, conversion time also increases. This limitation of high conversion time for high resolution is addressed by a reconfigurable programmable slope ADC. The reconfigurability in this ADC is achieved by changing the slope of ramp during conversion which is utilized to optimize its resolution and conversion time. The programmable slopes of ramp are obtained using programmed current sources which are made using low cost DACs and are calibrated to the required accuracy using a simple technique described in the paper. A two slope 12-bit ADC was designed and simulated using MultiSim 13.0, test results of which are presented in the paper. Using this method the conversion time is scaled down even at reduced clock frequency. Because of reduced clock frequency, the problems of noise pickup and high power dissipiation associated with high clock frequency are also avoided. It is also possible to use different clock frequencies during each slope for further optimization of resolution and conversion time.