Design of a low power static frequency divider

Frequency divider is an important unit in phase-locked loop (PLL) which is widely used in RF frequency synthesizer. The divider circuit has been identified as the main contributor to PLL power dissipation. Therefore, frequency divider with low power dissipation is necessary. The objectives of this work are to design a frequency divider with low power dissipation which is able to operate under low supply voltage using Silterra 0.13μm CMOS technology. This work also compares performance of the proposed frequency divider to the conventional frequency divider, which is implemented in MOSFET. The proposed frequency divider is based on TSPC topology. DTMOS and FBB techniques have been adopted in the proposed frequency divider to enable it operate at low supply voltage, results in low power dissipation. The performance of the proposed frequency divider in term of maximum operating frequency, supply voltage, power dissipation and phase noise have been compared to those of conventional frequency divider which is implemented using MOSFET. The result of this work has shown that the proposed DTMOS-FBB frequency divider is able to operate up to 2.5GHz from 0.6V supply voltage. It only dissipates 29μW of power. Compared to the MOSFET frequency divider, at the same operating frequency it dissipates 61 μW from 1.2V supply voltage. It is shown the proposed DTMOS-FBB frequency divider has reduced up to 52% of power dissipation when compared to MOSFET frequency divider.