A study on low power phase frequency detectors for delay locked loop

Delay Locked Loops (DLL) adapted in various applications due to its low power characteristics. Aggressive power demand in sensors, medical devices and new communications applications with embedded DLL has affected by Phase Frequency Detector (PFD) design techniques. This paper presents a review of various PFD in DLL design based on their main parameters including dynamic logic PFD topologies, PFD important parameters and issues total power consumption as well as their design trade-offs. This review paper gives a guideline to the future researchers for designing high speed and low power PFD.