Design and Implementation of a Digital Secure Code-Shifted Reference UWB Transmitter and Receiver

This paper presents the first compact hardware implementation of a digital code-shifted reference (CSR) ultra-wideband (UWB) transceiver. The security of the transmission is based on changing the physical properties of the transmission without the use of higher level security options. The software models of the designed transceiver are simulated and verified in both floating-point and fixed-point numerical representations. The synthesizable Verilog description of the transceiver architecture is simulated and verified against its fixed-point simulation model. The secure transceiver is implemented on our custom-developed field-programmable gate array (FPGA) board. The characteristic and implementation results of the secure transceiver architecture on the FPGA are presented. The bit error rate performance of the transceiver is measured in real time on the FPGA using an accurate on-chip Gaussian noise generator and is compared with that of the software simulation model. An ASIC architecture of the CSR-UWB transceiver is estimated to occupy 0.019 mm
²
and dissipate 0.63 mW from a 1.0 V supply while operating at 82 MHz in a standard 32-nm CMOS technology.