Dynamic Power Optimization Based on Formal Property Checking of Operations

Formal verification techniques for System-on-Chips (SoCs) have matured significantly over the last years. They can penetrate deeply into a design to exhibit complex functional dependencies between various design components in terms of detailed logic and temporal relationships. The purpose of this paper is to show how this knowledge can be leveraged to optimize the dynamic power consumptions of SoC modules. Starting from a set of SVA properties fulfilling the criterion of full functional coverage, this paper proposes a new approach to clock gating based on an operational design view as introduced by existing property checking methodologies. The paper shows how certain flip-flops can be identified that are irrelevant during certain times of specific operations and therefore can be clockgated. In an industrial case study savings in power consumption of 20 % were achieved demonstrating the great potential of the proposed approach.