Two-Step Residue Transfer Technique for High-Speed Pipeline A/Ds

We propose a two-step residue transfer technique for pipeline ADCs, that does not suffer from interleaving issues. The proposed technique is shown to be more power-efficient (for the same SNR) than the traditional residue generation technique in pipeline A/Ds, beyond a certain sampling speed. Circuit simulation results at the schematic level are given for a 57 dB SNDR (thermal noise included) 52 mW, 2.23 GS/s pipeline ADC in 65 nm CMOS. Consequently this technique extends the maximum conversion speed of a pipeline A/D converter without interleaving.